Pedro Benedicte
Biography
I am pursuing a PhD in Computer Architecture from UPC-BarcelonaTech. My research is done at Barcelona Supercomputing Center, focused on architectures for Real-Time Systems and Probabilistic Timing Analysis. My advisors are Dr. Francisco J. Cazorla, Dr. Jaume Abella and Dr. Carles Hernandez.
Degrees
I obtained a BSc in Informatics Engineering with a specialization in Computer Engineering and a MSc in Innovation and Research in Informatics with a specialization in High Performance Computing, both from UPC-BarcelonaTech. I spent the last year of my BSc in Northeastern University, in Boston.
My master thesis "On the Analysis of the Timing Behaviour
of Time Randomised Caches" was done under the supervision of Dr. Francisco J. Cazorla and Dr. Jaume Abella.
Current research
My current research focuses on the computer architecture of Real-Time Systems. Specifically, we aim to increase guaranteed performance in those systems by using techniques commonly found in High Performance Computers. In order to implement those features, we take advantage of Probabilistic Timing Analysis techniques.
Publications
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[DOI]
[PDF]
Performance Analysis and Optimization of Automotive GPUs
F. Mazzocchetti, P. Benedicte, H. Tabani, L. Kosmidis, J. Abella, F. J. Cazorla
International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019
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[DOI]
[PDF]
Locality-aware Cache Random Replacement Policies
P. Benedicte, C. Hernandez J. Abella, F. J. Cazorla
Journal of Systems Architecture (JSA), 2019
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[DOI]
[PDF]
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
P. Benedicte, C. Hernandez J. Abella, F. J. Cazorla
Design, Automation and Test in Europe (DATE), 2019
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[DOI]
[PDF]
Towards Limiting the Impact of Timing Anomalies in Complex Real-Time Processors
P. Benedicte, J. Abella, C. Hernandez, E. Mezzetti, F. J. Cazorla
Asia and South Pacific Design Automation Conference (ASPDAC), 2019
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[DOI]
[PDF]
HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET estimates in Multicore Real-Time Systems
P. Benedicte, C. Hernandez J. Abella, F. J. Cazorla
EUROMICRO Conference on Real-Time Systems (ECRTS), 2018
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[DOI]
RPR: A Random Replacement Policy with Limited Pathological Replacements
P. Benedicte, C. Hernandez J. Abella, F. J. Cazorla
ACM Symposium on Applied Computing (SAC), 2018
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[DOI]
[PDF]
Design and Integration of Hierarchical-Placement Multi-level Caches for Real-Time Systems
P. Benedicte, C. Hernandez, J. Abella, F. J. Cazorla
Design, Automation and Test in Europe (DATE), 2018
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[DOI]
[PDF]
A confidence assessment of WCET estimates for software time randomized caches
P. Benedicte, L. Kosmidis, E. QuiƱones, J. Abella, F. J. Cazorla
IEEE International Conference on Industrial Informatics (INDIN), 2016
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[DOI]
[PDF]
Modelling the confidence of timing analysis for time randomised caches
P. Benedicte, L. Kosmidis, E. QuiƱones, J. Abella, F. J. Cazorla
IEEE Symposium on Industrial Embedded Systems (SIES), 2016
Honors
- FPU Grant 2016-2020
- BSC Severo Ochoa Excellence Scholarship 2014-2016
- Winner team of the IV Spanish Parallel Programming Contest 2014
Team composition: Albert Segura, Pedro Benedicte
- Collaboration grant with the Computer Architecture department of UPC 2013
Contact
Mail: pedro@benedicte.org
LinkedIn
Google Scholar
Last updated: August 2019